Mentor Graphics

Boosting designs to a new level of accuracy

Whitepapers

Analogue design traditionally uses a bottom up design methodology. This approach can result in costly extra effort if system integration issues are found late in the design cycle.

In this whitepaper, Mentor Graphics explain a top down approach to circuit design, using Verilog-A which encourages early system level simulations to verify interface and integration issues. Benefits include:

•Perform behavioural modelling for faster runtimes and early system level simulations

•Special measurements with DNL, INL, and relative settling time

•Create complex input stimuli

•Create models of non-standard devices such as MEMS, image sensors, or TFTs

The whitepaper reviews:

•Behaviour modelling and modelling development

•Simulation runtimes for a PLL

•Signal blocks modelling

•SOA checks

whitepaper
Verilog-A
analogue design
top down approach
circuit design
early system level simulations
behavioural modelling
faster run times
MEMs
image sensors
TFTs
signal blocks modelling
https://www.mentor.com/uk/